May 25, 2026, Huawei’s latest chip technology

"Tao (τ) Law": Officially proposed at the ISCAS conference on May 25, 2026, it advocates improving the effective density and energy efficiency of transistors through means such as "logic folding" (vertical integration of multi-layer circuits), device-level delay compression, and Lingqu bus system interconnection. The goal is to reach the equivalent level of the 1.4nm process in 2031, rather than relying solely on process shrinkage. ‌Mobile Chip‌: ‌Kirin 2026‌ (expected to be released in the fall of 2026) is the first mobile phone SoC to fully adopt logic folding technology, achieving a step increase in transistor density and performance. The details of the process have not been disclosed, but it emphasizes "transcending the limitations of advanced processes." ‌AI computing power chip‌: ‌Ascend 950PR‌ (released in 2026Q1) is for prefill/inference, ‌Ascend 950DT‌ (to be released in 2026Q4) is for decoding/training They all support HIF8/fp8/mxfp4, 2TB/s Internet bandwidth, and self-developed HBM; the road signs are clear: Ascend 960 (2027Q4) and 970 (2028Q4) continue to double. ‌General Computing‌: ‌Kunpeng 950‌ (released in 2026Q1) is 96/192 core with The 192/384 core version supports confidential computing and super-node architecture, and is equipped with the Lingqu protocol to achieve hundreds of nanosecond-level interconnection and global unified memory. ‌Process Status‌: Limited by the external environment, Huawei has not disclosed the mass production information of self-developed logic chips using advanced processes (such as 3nm/2nm). The ‌Tao's Law" path clearly bypasses pure node competition‌ and focuses on system-architecture-packaging synergy (including Chiplet, 2.5D/3D integration potential). ‌‌<p class="marklang-paragraph" style="font-size:var(--cos-text-body-lg-higher);color:var(--cos-color-text);font-weight:var(--cos-font-regular);font-family:"">There is currently no public evidence that Huawei has released consumer-grade chips based on TSMC/Samsung's nodes below 3nm; the latest progress focuses on design methodology innovation (Tao's Law) + the Ascend 950 series has been released Column + To be released Kirin 2026‌. The autumn Kirin chip will be a key milestone in verifying the implementation of the "time micronization" path. ‌‌